The engineering problem
Four-person course project for ECNG3108 VLSI Design at AUC — full-custom transistor-level IC design in Cadence Virtuoso. My own block was the magnitude comparator; the rest was shared team work.
Design a low-power, transistor-level 4-bit ALU at a reduced 0.8 V supply while meeting the 20 MHz operating target.
Approach & contribution
Mazen designed and characterized the hybrid TG-PTL magnitude comparator in Spectre across EQ, GT and LT cases.
Contributed to the dual-Vt and dual block-gating strategy using a PMOS header and NMOS footer.
Malak A. Farid, Jannah M. Hella, Mazen and Youssef I. Mohammed formed the four-person team. Full integration and exhaustive verification are team results, not Mazen’s individual work.
Results & boundaries
Team pre-layout simulations verified all 14 operations at 65 nm, 0.8 V and a 20 MHz target.
Team results: 1.54 ns worst-case delay; 29–221 nW dynamic power per block; below 1.3 nW leakage per block.
The ALU reached pre-layout simulation only. No ALU physical layout, DRC/LVS, PEX or post-layout results are claimed.
Content basis: MAZEN_CONTEXT v1.3, 9 October 2026